Title : Extraction and Diagnosis of Submicron Defects
Candidate : Aymen LADHAR
Advisor : Pr. Mohamed Masmoudi
PhD : These Docteur-Ingénieur, National School of Engineers of Sfax - Tunisia
Speciality : Science and Technology
Defense : The defense date will be fixed later.

Abstract :
The rapid growth in semiconductor field results in an increasing complexity of digital circuits and parameter variations. Systematic defects are the major yield detractor in CMOS integrated circuits. Effective and precise diagnosis of these defects is crucial to improve yield and therefore to ensure a shorter time to market and cheaper product cost. This dissertation presents efficient techniques for three systematic defects extraction, which are based on the use of computer aided design tools. An accurate multiple faults diagnosis algorithm for the failure caused by each one of these systematic defects is also presented in this document.
An extra connection between two neighbored nodes, that should be not connected, can cause an unintentional connection inside an integrated circuit. This defect is known as bridging fault and can affect the cell and transistor routing. A technique to extract the netlist name of all the neighbored metal and polysilicon nodes is presented in this thesis report.
A defective contact can induce an imperfect circuit connection that can be modeled as a defect resistor between two circuit nodes that should be connected. Defective contacts provoke different sorts of open defects at the transistor level, depending upon their location in the circuit and the resistance values that they cause. A technique to extract all the contact (x, y) placements and the transistor names that they disconnect, when an open defect occurs, is also shown in this dissertation.
A defective via can cause an interconnect open defect disconnecting a set of logic gates to their drivers. In this dissertation, we present an efficient technique to extract the location and the name of disconnecting gates by each potential defective via.
Once the location of each defective site is determined, we use this physical information for the volume fault diagnosis. This dissertation presents a precise multiple faults diagnosis methodology for all the quoted defects. This approach diagnoses failing patterns one at a time and it allows the analysis of three types of multiple faults configuration. Conventional stuck-at fault model, associated with a ranking mechanism, are firstly applied to determine possible fault locations. However this location information does not inform whether the real defect is on the interconnecting wire or inside the library cell associated with the identified location. Consequently, in the diagnosis algorithm developed in this dissertation, we use the physical information extracted from the circuit layout to find out the adequate fault model that matches the failures observed on the tester.
Experiments on real circuits in production at STMicroelectronics confirm the scalability, performance, and resolution of the methodology developed in this dissertation to identify systematic defects.